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| Freescale Semiconductor, Inc. MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order number: MPC92432 Rev 0, 06/2004 Product Preview 1360 MHz Dual Output LVPECL Clock Synthesizer The MPC92432 is a 3.3V compatible, PLL based clock synthesizer targeted for high performance clock generation in mid-range to high-performance telecom, networking, and computing applications. With output frequencies from 21.25 MHz to 1360 MHz and the support of two differential PECL output signals, the device meets the needs of the most demanding clock applications. Features MPC92432 1360 MHz LOW VOLTAGE CLOCK SYNTHESIZER Freescale Semiconductor, Inc... * * * * * * * * * * * * * 21.25 MHz to 1360 MHz synthesized clock output signal Two differential, LVPECL-compatible high-frequency outputs Output frequency programmable through 2-wire I2C bus or parallel interface On-chip crystal oscillator for reference frequency generation Alternative LVCMOS compatible reference clock input Synchronous clock stop functionality for both outputs LOCK indicator output (LVCMOS) LVCMOS compatible control inputs Fully integrated PLL 3.3-V power supply 48-lead LQFP SiGe Technology Ambient temperature range: -40C to +85C SCALE 2:1 FA SUFFIX 48-LEAD LQFP PACKAGE CASE 932 Applications * Programmable clock source for server, computing, and telecommunication systems * Frequency margining * Oscillator replacement Functional Description The MPC92432 is a programmable high-frequency clock source (clock synthesizer). The internal PLL generates a high-frequency output signal based on a low-frequency reference signal. The frequency of the output signal is programmable and can be changed on the fly for frequency margining purpose. The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. Alternatively, a LVCMOS compatible clock signal can be used as a PLL reference signal. The frequency of the internal crystal oscillator is divided by a selectable divider and then multiplied by the PLL. The VCO within the PLL operates over a range of 1360 to 2720 MHz. Its output is scaled by a divider that is configured by either the I2C or parallel interfaces. The crystal oscillator frequency fXTAL, the PLL pre-divider P, the feedback-divider M, and the PLL post-divider N determine the output frequency. The feedback path of the PLL is internal. The PLL post-divider N is configured through either the I2C or the parallel interfaces, and can provide one of six division ratios (2, 4, 8, 16, 32, 64). This divider extends the performance of the part while providing a 50% duty cycle. The high-frequency outputs, QA and QB, are differential and are capable of driving a pair of transmission lines terminated 50 to VCC - 2.0 V. The second high-frequency output, QB, can be configured to run at either 1x or 1/2x of the clock frequency or the first output (QA). The positive supply voltage for the internal PLL is separated from the power supply for the core logic and output drivers to minimize noise induced jitter. The configuration logic has two sections: I2C and parallel. The parallel interface uses the values at the M[9:0], NA[2:0], NB, and P parallel inputs to configure the internal PLL dividers. The parallel programming interface has priority over the serial I2C interface. The serial interface is I2C compatible and provides read and write access to the internal PLL configuration registers. The lock state of the PLL is indicated by the LVCMOS-compatible LOCK outputs. This document contains certain information on a new product. Specifications and information herein are subject to change without notice. (c) Motorola, Inc. 2004 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MPC92432 REF_CLK XTAL1 XTAL2 REF_SEL TEST_EN SDA SCL ADR[1:0] PLOAD M[9:0] NA[2:0] NB P CLK_STOPx BYPASS MR XTAL fREF /P PLL fVCO /NA fQA QA fQB /NB QB /M PLL Configuration Registers I2C Control LOCK Freescale Semiconductor, Inc... Figure 1. MPC92432 -- Generic Logic Diagram TEST_EN 25 24 23 22 21 20 19 36 35 34 33 32 31 30 29 28 27 GND NA2 NA1 NA0 PLOAD VCC MR SDA SCL ADR1 ADR0 P LOCK 26 GND GND VCC VCC VCC QA QA QB QB NB 37 38 39 40 41 42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 9 10 11 12 M9 M8 M7 M6 M5 GND M4 M3 M2 M1 M0 VCC MPC92432 18 17 16 15 14 13 CLK_STOPA CLK_STOPB It is recommended to use an external RC filter for the analog VCC_PLL supply pin. Please see the application section for details. REF_CLK BYPASS VCC VCC GND REF_SEL GND XTAL1 2 MOTOROLA VCC_PLL Figure 2. 48-Lead Package Pinout (Top View) TIMING SOLUTIONS For More Information On This Product, Go to: www.freescale.com XTAL2 Freescale Semiconductor, Inc. MPC92432 Table 1. Signal Configuration Pin XTAL1, XTAL2 REF_CLK REF_SEL QA QB LOCK M[9:0] NA[2:0] NB I/O Input Input Input Output Output Output Input Input Input Input Input I/O Input Input Input Input Input Input Supply Supply Analog LVCMOS LVCMOS Differential LVPECL Differential LVPECL LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Ground VCC VCC Type Crystal oscillator interface PLL external reference input Selects the reference clock input High frequency clock output High frequency clock output PLL lock indicator PLL feedback divider configuration PLL post-divider configuration for output QA PLL post-divider configuration for output QB PLL pre-divider configuration Selects the programming interface I2C data I2C clock Selectable two bits of the I2C slave address Selects the static circuit bypass mode Factory test mode enable. This input must be set to logic low level in all applications of the device. Output Qx disable in logic low state Device master reset Negative power supply Positive power supply for the PLL (analog power supply). It is recommended to use an external RC filter for the analog power supply pin VCC_PLL. Positive power supply for I/O and core Function Freescale Semiconductor, Inc... P P_LOAD SDA SCL ADR[1:0] BYPASS TEST_EN CLK_STOPx MR GND VCC_PLL VCC Supply TIMING SOLUTIONS 3 MOTOROLA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MPC92432 Table 2. Function Table Control Inputs REF_SEL M[9:0] NA[2:0] NB P PLOAD 1 01 1111 0100b2 010 0 1 0 Selects REF_CLK input as PLL reference clock Selects the XTAL interface as PLL reference clock Default1 0 1 PLL feedback divider (10-bit) parallel programming interface PLL post-divider parallel programming interface. See Table 9 PLL post-divider parallel programming interface. See Table 10 PLL pre-divider parallel programming interface. See Table 8 Selects the parallel programming interface. The internal PLL divider settings (M, NA, NB and P) are equal to the setting of the hardware pins. Leaving the M, NA, NB and P pins open (floating) results in a default PLL configuration with fOUT = 250 MHz. See application/programming section. Address bit = 0 See Programming the MPC92432 Selects the serial (I2C) programming interface. The internal PLL divider settings (M, NA, NB and P) are set and read through the serial interface. Freescale Semiconductor, Inc... ADR[1:0] SDA, SCL BYPASS 00 Address bit = 1 1 PLL function bypassed fQA=fREF/ NA and fQB=fREF/ (NA* NB) Application mode. Test mode disabled. Output Qx is disabled in logic low state. Synchronous disable is only guaranteed if NB = 0. PLL function enabled fQA = (fREF/ P) * M / NA and fQB = (fREF / P) * M / (NA * NB) Factory test mode is enabled Output Qx is synchronously enabled TEST_EN CLK_STOPx MR 0 1 The device is reset. The output frequency is zero and The PLL attempts to lock to the reference signal. The tLOCK specification applies. the outputs are asynchronously forced to logic low state. After releasing reset (upon the rising edge of MR and independent on the state of PLOAD), the MPC92432 reads the parallel interface (M, NA, NB and P) to acquire a valid startup frequency configuration. See application/programming section. Outputs LOCK 1. 2. PLL is not locked PLL is frequency locked Default states are set by internal input pull-up or pull-down resistors of 75 k If fREF = 16 MHz, the default configuration will result in a output frequency of 250 MHz MOTOROLA 4 TIMING SOLUTIONS For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MPC92432 Table 3. General Specifications Symbol VTT MM HBM LU CIN JA Characteristics Output Termination Voltage ESD Protection (Machine model) ESD Protection (Human body model) Latch-Up Immunity Input Capacitance Thermal Resistance Junction to Ambient JESD 51-3, single layer test board Min -- 200 2000 200 -- -- Typ VCC - 2 -- -- -- 4.0 -- Max -- -- -- -- -- TBD Unit V V V mA pF C/W Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min -- -- TBD C/W MIL-SPEC 883E Method 1012.1 Inputs Condition Freescale Semiconductor, Inc... JESD 51-6, 2S2P multilayer test board JC LQFP 32 Thermal Resistance Junction to Case Table 4. Absolute Maximum Ratings1 Symbol VCC VIN VOUT IIN IOUT TS 1. Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage temperature Characteristics Min -0.3 -0.3 -0.3 -- -- -65 Max 3.9 VCC+0.3 VCC+0.3 20 50 125 Unit V V V mA mA C Condition Absolute maximum continuos ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. TIMING SOLUTIONS 5 MOTOROLA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MPC92432 Table 5. DC Characteristics (VCC = 3.3 V 5%, TJ = -40C to +85C) Symbol Characteristics Min Typ Max Unit Condition LVCMOS Control Inputs (M[9:0], N[2:0], ADDR[1:0], NB, P, CLK_STOPx, BYPASS, MR, REF_SEL, TEST_EN, PLOAD) VIH VIL IIN Input High Voltage Input Low Voltage Input Current1 2.0 -- -- -- -- -- VCC + 0.3 0.8 200 V V A LVCMOS LVCMOS VIN = VCC or GND I2C Inputs (SCL, SDA) VIH VIL IIN Input High Voltage Input Low Voltage Input Current 2.0 -- -- -- -- -- VCC + 0.3 0.8 10 V V A LVCMOS LVCMOS Freescale Semiconductor, Inc... LVCMOS Output (LOCK) VOH VOL Output High Voltage Output Low Voltage 2.4 -- -- -- -- 0.4 V V IOH = -4 mA IOL = 4 mA I2C Open-Drain Output (SDA) VOL Input Low Voltage -- -- 0.4 V IOL = 4 mA Differential Clock Output QA, QB2 VOH VOL VO(P-P) Output High Voltage Output Low Voltage Output Peak-to-Peak Voltage VCC - 1.05 VCC - 1.95 0.5 -- -- 0.6 VCC - 0.74 VCC - 1.60 1.0 V V V LVPECL LVPECL Supply current ICC_PLL ICC 1. 2. Maximum PLL Supply Current Maximum Supply Current -- -- -- -- TBD TBD mA mA VCC_PLL Pins All VCC Pins Inputs have pull-down resistors affecting the input current. Outputs terminated 50 to VTT = VCC - 2 V MOTOROLA 6 TIMING SOLUTIONS For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MPC92432 Table 6. AC Characteristics (VCC = 3.3 V 5%, TJ = -40C to +85C)1 2 Symbol fXTAL fREF fVCO fMAX Characteristics Crystal Interface Frequency Range FREF_EXT Reference Frequency Range VCO Frequency Range3 Output Frequency4 N= /2 N= /4 N= /8 N= /16 N= /32 N= /64 Min 15 15 1360 680 340 170 85 42.5 21.25 0 (P_LOAD) 50 45 Same frequency Different frequency -- -- 0.05 -- TFOUT 0.5 * TFOUT N= /2 N= /4 N= /8 N= /16 N= /32 N= /64 fOUT = 250 MHz Any other frequency -- -- -- -- -- -- -- -- -- Typ 16 -- -- -- -- -- -- -- -- -- -- 50 -- 50 -- -- -- -- -- -- -- -- -- -- -- -- -- 55 25 0.3 250 2 * TFOUT 1.5 * TFOUT TBD TBD 25 25 TBD TBD 10 TBD 10 ps ps ps ps ps ps ps ps ms Max 20 20 2720 1360 680 340 170 85 42.5 0.4 Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz ns % ps ps ns ns 20% to 80% CL = 400 pF T = period of Qx T = period of Qx Condition fSCL Serial Interface (I2C) Clock Frequency Minimum Pulse Width Output Duty Cycle Output-to-Output Skew Output Rise/Fall Time (QA, QB) Output Rise/Fall Time (SDA) Output Enable Time (CLKSTOPx to QA, QB) Output Enable Time (CLKSTOPx to QA, QB) Cycle-to-Cycle Jitter Freescale Semiconductor, Inc... tP,MIN DC tSK(O) tr, tf tr, tf tP_EN tP_DIS tJIT(CC) tJIT(CC) tLOCK 1. 2. 3. 4. Period Jitter (RMS) Maximum PLL Lock Time AC specifications are subject to change AC characteristics apply for parallel output termination of 50 to VTT The input frequency fXTAL, the PLL divider M and P must match the VCO frequency range: fVCO = fXTAL * M / P. The feedback divider M is limited to 170 <= M <= 340 (for P = 2) and 340 <= M <= 680 (for P = 4) for stable PLL operation Output frequency for QA, QB if NB=0. With NB=1 the QB output frequency is half of the QA output frequency TIMING SOLUTIONS 7 MOTOROLA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MPC92432 APPLICATION INFORMATION Output Frequency Configuration The MPC92432 is a programmable frequency source (synthesizer) and supports an output frequency range of 21.25 - 1360 MHz. The output frequency fOUT is a function of the reference frequency fREF and the three internal PLL dividers P, M, and N. fOUT can be represented by this formula: fOUT = (fREF / P) * M / (NA, B) (1) Table 7. Frequency Ranges (fREF = 16 MHz) fOUT (QA) [MHz] 680 - 1360 NA NA=2 NA=4 NA=8 NA=16 NA=32 NA=64 M 170 - 340 340 - 680 170 - 340 340 - 680 170 - 340 340 - 680 170 - 340 340 - 680 170 - 340 340 - 680 170 - 340 340 - 680 P 2 4 2 4 2 4 2 4 2 4 2 4 G [MHz] 4 2 2 1 1 0.5 0.5 0.25 0.25 0.125 0.125 0.0625 340 - 680 Freescale Semiconductor, Inc... The M, N and P dividers require a configuration by the user to achieve the desired output frequency. The output divider, NA, determines the achievable output frequency range (see Table 7). The PLL feedback-divider M is the frequency multiplication factor and the main variable for frequency synthesis. For a given reference frequency fREF, the PLL feedback-divider M must be configured to match the specified VCO frequency range in order to achieve a valid PLL configuration: fVCO = (fREF / P) * M and 1360 fVCO 2720 (2) (3) 170 - 340 85 - 170 42.5 - 85 21.25 - 42.5 The output frequency may be changed at any time by changing the value of the PLL feedback divider M. The smallest possible output frequency change is the synthesizer granularity G (difference in fOUT when incrementing or decrementing M). At a given reference frequency, G is a function of the PLL predivider P and post-divider N: G = fREF / (P * NA,B) (4) Example Output Frequency Configuration If a reference frequency of 16 MHz is available, an output frequency at QA of 250 MHz and a small frequency granularity is desired, the following steps would be taken to identify the appropriate P, M, and N configuration: 1. Use Table 7 to select the output divider, NA, that matches the desired output frequency or frequency range. According to Table 7, a target output frequency of 250 MHz falls in the fOUT range of 170 to 340 MHz and requires to set NA = 8 Calculate the VCO frequency fVCO = fOUT * NA, which is 2000 MHz in this example. Determine the PLL feedback divider: M = fVCO / P. The smallest possible output granularity in this example calculation is 500 kHz (set P = 4). M calculates to a value of 2000 / 4 = 500. Configure the MPC92432 with the obtained settings: M[9:0] = 0111110100b (binary number for M=500) NA[2:0] = 010 P=1 NB = 0 5. (/8 divider, see Table 9) (/4 divider, see Table 8) (fOUT, QB = fOUT, QA) The NB divider configuration determines if the output QB generates a 1:1 or 2:1 frequency copy of the QA output signal. The purpose of the PLL pre-divider P is to situated the PLL into the specified VCO frequency range fVCO (in combination with M). For a given output frequency, P = 4 results in a smaller output frequency granularity G, P = 2 results a larger output frequency granularity G and also increases the PLL bandwidth compared to the P = 2 setting. The following example illustrates the output frequency range of the MPC92432 using a 16-MHz reference frequency. 2. 3. 4. Use either parallel or serial interface to apply the setting. The I2C configuration byte for this examples are: PLL_H=01010010b and PLL_L=11110100b. See Table 14 and Table 15 for register maps. MOTOROLA 8 TIMING SOLUTIONS For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MPC92432 PLL Divider Configuration Table 8. Pre-PLL Divider P P 0 1 Value fREF / 2 fREF / 4 Upon startup, when the device reset signal is released (rising edge of the MR signal), the device reads its startup configuration through the parallel interface and independent on the state of PLOAD. It is recommended to provide a valid PLL configuration for startup. If the parallel interface pins are left open, a default PLL configuration will be loaded. After the lowto-high transition of PLOAD, the configuration pins have no more effect and the configuration registers are made accessible through the serial interface. Table 11. PLL Feedback-Divider Configuration (M) Feedback Divider M Pin Default 9 M9 0 8 M8 1 7 M7 1 6 M6 1 5 M5 1 4 M4 1 3 M3 0 2 M2 1 1 M1 0 0 M0 0 Table 9. Post-PLL Divider NA NA0 0 0 NA1 0 0 1 1 0 0 NA2 0 1 0 1 0 1 fOUT (QA) fVCO / 2 fVCO / 4 fVCO / 8 fVCO / 16 fVCO / 32 fVCO / 64 Freescale Semiconductor, Inc... 0 0 1 1 Table 12. PLL Pre/Post-Divider Configuration (N, P) Post-D. NA Pin 2 NA2 0 1 NA1 1 0 NA0 1 Post-D. NB Pin Default NB NB 0 Pre-D. P Pin Default P P 1 Table 10. Post-PLL Divider NB NB 0 1 Value fOUT, QB = fOUT, QA fOUT, QB = fOUT, QA / 2 Default Programming the MPC92432 The MPC92432 has a parallel and a serial configuration interface. The purpose of the parallel interface is to directly configure the PLL dividers through hardware pins without the overhead of a serial protocol. At device startup, the device always obtains an initial PLL frequency configuration through the parallel interface. The parallel interface does not support reading the PLL configuration. The serial interface is I2C compatible. It allows reading and writing devices settings by accessing internal device registers. The serial interface is designed for host-controller access to the synthesizer frequency settings for instance in frequencymargining applications. Using the Parallel Interface The parallel interface supports write-access to the PLL frequency setting directly through 15 configuration pins (P, M[9:0], NA[2:0], and NB). The parallel interface must be enabled by setting PLOAD to logic low level. During PLOAD = 0, any change of the logical state of the P, M[9:0], NA[2:0], and NB pins will immediately affect the internal PLL divider settings, resulting in a change of the internal VCOfrequency and the output frequency. The parallel interface mode disables the I2C write-access to the internal registers; however, I2C read-access to the internal configuration registers is enabled. Using the I2C Interface PLOAD = 1 enables the programming and monitoring of the internal registers through the I2C interface. Device register access (write and read) is possible through the 2-wire interface using SDA (configuration data) and SCL (configuration clock) signals. The MPC92432 acts as a slave device at the I2C bus. For further information on I2C it is recommended to refer to the I2C bus specification (version 2.1). PLOAD = 0 disables the I2C-write-access to the configuration registers and any data written into the register is ignored. However, the MPC92432 is still visible at the I2C interface and I2C transfers are acknowledged by the device. Read-access to the internal registers during PLOAD = 0 (parallel programming mode) is supported. Note that the device automatically obtains a configuration using the parallel interface upon the release of the device reset (rising edge of MR) and independent on the state of PLOAD. Changing the state of the PLOAD input is not supported when the device performs any transactions on the I2C interface. Programming Model and Register Set The synthesizer contains two fully accessible configuration registers (PLL_L and PLL_H) and a write-only command register (CMD). Programming the synthesizer frequency through the I2C interface requires two steps: 1) writing a valid PLL configuration to the configuration registers and 2) loading the registers into the PLL by an I2C command. The PLL frequency is affected as a result of the second step. TIMING SOLUTIONS 9 MOTOROLA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MPC92432 This two-step procedure can be performed by a single I2C transaction or by multiple, independent I2C transactions. An alternative way to achieve small PLL frequency changes is to use the increment or decrement commands of the synthesizer, which have an immediate effect on the PLL frequency. Synthesizer - PLL P N M LOAD/GET PLL_L (R/W) PLL_H (R/W) 0x00 0x01 CMD (W) 0xF0 I2 C Registers conditions such as the VCO frequency range. Applying the INC and DEC commands could result in invalid VCO frequencies (VCO frequency beyond lock range). Register Maps Configuration Latches Table 13. Configuration Registers Address 0x00 0x01 Name PLL_L PLL_H Content Least significant 8 bits of M Most significant 2 bits of M, P, NA, NB, and lock state Command register (write only) Access R/W R/W I2C Access 0xF0 CMD W only Freescale Semiconductor, Inc... Figure 3. I C Mode Register Set Figure 3 illustrates the synthesizer register set. PLL_L and PLL_H store a PLL configuration and are fully accessible (Read/Write) by the I2C bus. CMD (Write only) accepts commands (LOAD, GET, INC, DEC) to update registers and for direct PLL frequency changes. Set the synthesizer frequency: 1) Write the PLL_L and PLL_H registers with a new configuration (see Table 14 and Table 15 for register maps) 2) Write the LOAD command to update the PLL dividers by the current PLL_L, PLL_H content. Read the synthesizer frequency: 1) Write the GET commands to update the PLL_L, PLL_H registers by the PLL divider setting 2) Read the PLL_L, PLL_H registers through I2C Change the synthesizer frequency in small steps: 1) Write the INC or DEC command to change the PLL frequency immediately. Repeat at any time if desired. LOAD and GET are inverse command to each other. LOAD updates the PLL dividers and GET updates the configuration registers. A fast and convenient way to change the PLL frequency is to use the INC (increment M) and DEC (decrement M) commands of the synthesizer. INC (DEC) directly increments (decrements) the PLL-feedback divider M and immediately changes the PLL frequency by the smallest step G (see Table 7 for the frequency granularity G). The INC and DEC commands are designed for multiple and rapid PLL frequency changes as required in frequency margining applications. INC and DEC do not require the user to update the PLL dividers by the LOAD command, INC and DEC do not update the PLL_L and PLL_H registers either (use LOAD for an initial PLL divider setting and, if desired, use GET to read the PLL configuration). Note that the synthesizer does not check any boundary Table 15. PLL_H (0x01, R/W) Register Bit Name 7 M9 6 M8 5 NA2 4 NA1 3 NA0 2 NB 1 P 0 LOCK 2 Register 0x00 (PLL_L) contains the least significant bits of the PLL feedback divider M. Table 14. PLL_L (0x00, R/W) Register Bit Name 7 M7 6 M6 5 M5 4 M4 3 M3 2 M2 1 M1 0 M0 Register content: M[7:0] PLL feedback-divider M, bits 7-0 Register 0x01 (PLL_H) contains the two most significant bits of the PLL feedback divider M, four bits to control the PLL postdividers N and the PLL pre-divider P. The bit 0 in PLL_H register indicates the lock condition of the PLL and is set by the synthesizer automatically. The LOCK state is a copy of the PLL lock signal output (LOCK). A write-access to LOCK has no effect. Register content: M[9:8] NA[2:0] NB P LOCK PLL feedback-divider M, bits 9-8 PLL post-divider NA, see Table 9 PLL post-divider NB, see Table 10 PLL pre-divider P, see Table 8 Copy of LOCK output signal (read-only) Note that the LOAD command is required to update the PLL dividers by the content of both PLL_L and PLL_H registers. Register 0xF0 (CMD) is a write-only command register. The purpose of CMD is to provide a fast way to increase or decrease the PLL frequency and to update the registers. The register accepts four commands, INC (increment M), DEC (decrement M), LOAD and GET (update registers). It is MOTOROLA 10 TIMING SOLUTIONS For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MPC92432 recommended to write the INC, DEC commands only after a valid PLL configuration is achieved. INC and DEC only affect the M-divider of the PLL (PLL feedback). Applying INC and DEC commands can result in a PLL configuration beyond the specified lock range and the PLL may loose lock. The MPC92432 does not verify the validity of any commands such as LOAD, INC, and DEC. The INC and DEC commands change the PLL feedback divider without updating PLL_L and PLL_H. Table 16. CMD (0xF0): PLL Command (Write-Only) Command INC DEC Op-Code xxxx0001b (0x01) xxxx0010b (0x02) xxxx0100b (0x04) xxxx1000b (0x08) Description Increase internal PLL frequency M:=M+1 Decrease internal PLL frequency M:=M-1 Update the PLL divider config. PLL divider M, N, P:=PLL_L, PLL_H Update the configuration registers PLL_L, PLL_H:=PLL divider M, N, P Table 17. PLL Configuration in Parallel and Serial Modes PLL Configuration M[9:0] NA[2:0] NB P LOCK status Parallel Set pins M9-M0 Set pins NA2...NA0 Set pin NB Set bit P in PLL_H LOCK pin 26 Serial (Registers PLL_L, PLL_H) M[9:0] (R/W) NA[2:0] (R/W) NB (R/W) P (R/W) LOCK (Read only) Programming the I2C Interface Table 18. I2C Slave Address Bit Value 7 1 6 0 5 1 4 1 3 0 2 Pin ADR1 1 Pin ADR0 0 R/W Freescale Semiconductor, Inc... LOAD GET I2C -- Register Access in Parallel Mode The MPC92432 supports the configuration of the synthesizer through the parallel interlace (PLOAD = 0) and serial interface (PLOAD = 1). Register contents and the divider configurations are not changed when the user switches from parallel mode to serial mode. However, when switching from serial mode to parallel mode, the PLL dividers immediately reflect the logical state of the hardware pins M[9:0], NA[2:0], NB, and P. Applications using the parallel interface to obtain a PLL configuration can use the serial interface to verify the divider settings. In parallel mode (PLOAD = 0), the MPC92432 allows read-access to PLL_L and PLL_H through I2C (if PLOAD = 0, the current PLL configuration is stored in PLL_L, PLL_H. The GET command is not necessary and also not supported in parallel mode). After changing from parallel to serial mode (PLOAD = 1), the last PLL configuration is still stored in PLL_L, PLL_H. The user now has full write and read access to both configuration registers through the I2C bus and can change the configuration at any time. The 7-bit I2C slave address of the MPC92432 synthesizer is a combination of a 5-bit fixed addresses and two variable bits which are set by the hardware pins ADR[1:0]. Bit 0 of the MPC92432 slave address is used by the bus controller to select either the read or write mode.'0' indicates a transmission (I2C-WRITE) to the MPC92432.'1' indicates a request for data (I2C-READ) from the synthesizer. The hardware pins ADR1 and ADR0 and should be individually set by the user to avoid address conflicts of multiple MPC92432 devices on the same I2C bus. Write Mode (R/W = 0) The configuration registers are written by the bus controller by the initiation of a write transfer with the MPC92432 slave address (first byte), followed by the address of the configuration register (second byte: 0x00, 0x01 or 0xF0), and the configuration data byte (third byte). This transfer may be followed by writing more registers by sending the configuration register address followed by one data byte. Each byte sent by the bus controller is acknowledged by the MPC92432. The transfer ends by a stop bit sent by the bus controller. The number of configuration data bytes and the write sequence are not restricted. Table 19. Complete Configuration Register Write Transfer 1 bit Start 7 bits Slave address 10110xx1 Master Master 1 bit R/W 0 Mast Slave 1 bit ACK 8 bits &PLL_H 0x01 Master Slave 1 bit ACK 8 bits Config-Byte 1 Data Master Slave 1 bit ACK 8 bits &PLL_L 0x00 Master Slave 1 bit ACK 8 bits Config-Byte 2 Data Master Slave Mast 1 bit ACK 1 bit Stop 1. xx = state of ADR1, ADR0 pins TIMING SOLUTIONS 11 MOTOROLA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MPC92432 Read Mode (R/W = 1) The configuration registers are read by the bus controller by the initiation of a read transfer. The MPC92432 supports read transfers immediately after the first byte without a change in the transfer direction. Immediately after the bus controller sends the slave address, the MPC92432 acknowledges and then sends both configuration register PLL_L and PLL_H (back-to-back) to the bus controller. The CMD register cannot be read. In order to read the two synthesizer registers and the current PLL configuration setting, the user can 1) read PLL_L, PLL_H, write the GET command (loads the current configuration into PLL_L, PLL_H) and read PLL_L, PLL_H again. Note that the PLL_L, PLL_H registers and divider settings may not be equivalent after the following cases: a. b. c. Writing the INC command Writing the DEC command Writing PLL_L, PLL_H registers with a new configuration and not writing the LOAD command. Table 20. Configuration Register Read Transfer 1 bit 7 bits Slave address 10110xx Master Master 1 1 bit R/W 1 Mast 1 bit ACK 8 bits PLL_L Data 1 bit ACK 8 bits PLL_H Data 1 bit ACK 1 bit Stop Freescale Semiconductor, Inc... Start Slave Slave Mast Slave Master Slave 1. xx = state of ADR1, ADR0 pins Device Startup General Device Configuration It is recommended to reset the MPC92432 during or immediately after the system powers up (MR = 0). The device acquires an initial PLL divider configuration through the parallel interface pins M[9:0], NA[2:0], N, and P1 with the low-to-high transition of MR2. PLL frequency lock is achieved within the specified lock time (tLOCK) and is indicated by an assertion of the LOCK signal which completes the startup procedure. It is recommended to disable the outputs (CLK_STOPx = 0) until PLL lock is achieved to suppress output frequency transitions. The output frequency can be reconfigured at any time through either the parallel or the serial interface. Note that a PLL configuration obtained by the parallel interface can be read through I2C independent on the current programming mode (parallel or serial). Refer to I2C -- Register Access in Parallel Mode for additional information on how to read a PLL startup configuration through the I2C interface. Start-Up Using the Serial (I2C) Interface VCC MR P, M, N PLOAD LOCK CLK_STOPx QA, QB Disabled (Low) tPLH 2C Stable & Valid Selects I2C Acquiring Lock PLL Lock Active Figure 4. Start-Up Using I Interface Starting-Up Using the Parallel Interface The simplest way to use the MPC92432 is through the parallel interface. The serial interface pins (SDA, SDL, and ADDR[1:0]) can be left open and PLOAD is set to logic low. After the release of MR and at any other time the PLL/output frequency configuration is directly set to through the M[9:0], NA[2:0], NB, and P pins. Set PLOAD = 1, CLK_STOPx = L and leave the parallel interface pins (M[9:0], NA[2:0], N, and P) open. The PLL dividers are configured by the default configuration at the lowto-high transition of MR. This initial PLL configuration can be reprogrammed to the final VCO frequency at any time through the serial interface. After the PLL achieved lock at the desired VCO frequency, enable the outputs by setting CLK_STOPx = H. PLL lock and re-lock (after any configuration change through M or P) is indicated by LOCK being asserted. 1. The parallel interface pins M[9:0], NA[2:0], N, and P may be left open (floating). In this case the initial PLL configuration will have the default setting of M = 500, P = 1, NA[2:0] = 010, NB = 0, resulting in an internal VCO frequency of 2000 MHz (fref = 16 MHz) and an output frequency of 250 MHz. 2. The initial PLL configuration is independent on the selected programming mode (PLOAD low or high) MOTOROLA 12 TIMING SOLUTIONS For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MPC92432 LOCK Detect The LOCK detect circuitry indicates the frequency-lock status of the PLL by setting and resetting the pin LOCK and register bit LOCK simultaneously. The LOCK status is asserted after the PLL acquired frequency lock during the startup and is immediately deasserted when the PLL lost lock, for instance when the reference clock is removed. The PLL may also loose lock when the PLL feedback-divider M or pre-divider P is changed or the DEC/INC command is issued. The PLL may not loose lock as a result of slow reference frequency changes. In any case of loosing LOCK, the PLL attempts to re-lock to the reference frequency. LOCK and re-lock of the PLL is indicated by the LOCK signal after a delay of TBD cycles to prevent signaling temporary PLL locks during frequency transitions. Output Clock Stop Asserting CLK_STOPx will stop the respective output clock in logic low state. The CLK_STOPx control is internally synchronized to the output clock signal, therefore, enabling and disabling outputs does not produce runt pulses. See Figure 5.The clock stop controls of the QA and QB outputs are independent on each other. If the QB runs at half of the QA output frequency and both outputs are enabled at the same time, the first clock pulse of QA may not appear at the same time of the first QB output. (See Figure 6.) Concident rising edges of QA and QB stay synchronous after the assertion and de-assertion of the CLK_STOPx controls. Asserting MR always resets the output divider to a logic low output state, with the risk of producing an output runt pulse. Freescale Semiconductor, Inc... CLK_STOPx (Enable) (Disable) (Enable) Qx tP_DIS tP_EN Figure 5. Clock Stop Timing for NB = 0 (fQA = fQB) CLK_STOPA,B (Enable) (Disable) (Enable) QA QB Figure 6. Clock Stop Timing for NB = 1 (fQA = 2 fQB) TIMING SOLUTIONS 13 MOTOROLA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MPC92432 Frequency Operating Range Table 21. MPC92432 Frequency Operating Range for P = 2 fVCO [MHz] (Parameter: fREF in MHz) M 170 180 190 200 210 220 M[9:0] 0010101010 0010110100 0010111110 0011001000 0011010010 0011011100 0011100110 0011110000 0011111010 0100000100 0100001110 0100011000 0100100010 0100101100 0100110110 0101000000 0101001010 0101010100 1425 1500 1575 1650 1725 1800 1875 1950 2025 2100 2175 2250 2325 2400 2475 2550 15 16 1360 1440 1520 1600 1680 1760 1840 1920 2000 2080 2160 2240 2320 2400 2480 2560 2640 2720 18 1530 1620 1710 1800 1890 1980 2070 2160 2250 2340 2430 2520 2610 2700 20 1700 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 2 680 720 760 800 840 880 920 960 1000 1040 1080 1120 1160 1200 1240 1280 1320 1360 Output Frequency for fXTAL = 16 MHz (Parameter N) 4 340 360 380 400 420 440 460 480 500 520 540 560 580 600 620 640 660 680 8 170 180 190 200 210 220 230 240 250 260 270 280 290 300 310 320 330 340 16 85 90 95 100 105 110 115 120 125 130 135 140 145 150 155 160 165 170 32 42.50 45.00 47.50 50.00 52.50 55.00 57.50 60.00 62.50 65.00 67.50 70.00 72.50 75.00 77.50 80.00 82.50 85.00 64 21.25 22.50 23.75 25.00 26.25 27.50 28.75 30.00 31.25 32.50 33.75 35.00 36.25 37.50 38.75 40.00 41.25 42.50 Freescale Semiconductor, Inc... 230 240 250 260 270 280 290 300 310 320 330 340 MOTOROLA 14 TIMING SOLUTIONS For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MPC92432 Table 22. MPC92432 Frequency Operating Range for P = 4 fVCO [MHz] (Parameter: fREF in MHz) M 340 350 360 370 380 390 400 410 M[9:0] 0101010100 0101011110 0101101000 0101110010 0101111100 0110000110 0110010000 0110110010 0110100100 0110101110 0110111000 0111000010 0111001100 0111010110 0111100000 0111101010 0111110100 0111111110 1000001000 1000010010 1000011100 1000100110 1000110000 1000111010 1001000100 1001001110 1001011000 1001100010 1001101100 1001110110 1010000000 1010001010 0010010100 1010011110 1010101000 1387.5 1425.0 1462.5 1500.0 1537.5 1575.0 1612.5 1650.0 1687.5 1725.0 1762.5 1800.0 1837.5 1875.0 1912.5 1950.0 1987.5 2025.0 2062.5 2100.0 2137.5 2175.0 2212.5 2250.0 2287.5 2325.0 2362.5 2400.0 2437.5 2475.0 2512.5 2550.0 15 16 1360 1400 1440 1480 1520 1560 1600 1640 1680 1720 1760 1800 1840 1880 1920 1960 2000 2040 2080 2120 2160 2200 2240 2280 2320 2360 2400 2440 2480 2520 2560 2600 2640 2680 2720 18 1530 1575 1620 1665 1710 1755 1800 1845 1890 1935 1980 2025 2070 2115 2160 2205 2250 2295 2340 2475 2520 2565 2610 2700 20 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 2650 2700 2 680 700 720 740 760 780 800 820 840 860 880 900 920 940 960 980 1000 1020 1040 1060 1080 1100 1120 1140 1160 1180 1200 1220 1240 1260 1280 1300 1320 1340 1360 Output Frequency for fXTAL = 16 MHz (Parameter N) 4 340 350 360 370 380 390 400 410 420 430 440 450 460 470 480 490 500 510 520 530 540 550 560 570 580 590 600 610 620 630 640 650 660 670 680 8 170 175 180 185 190 195 200 205 210 215 220 225 230 235 240 245 250 255 260 265 270 285 280 285 290 295 300 305 310 315 320 325 330 335 340 16 85.0 87.5 90.0 92.5 95.0 97.5 100.0 102.5 105.0 107.5 110.0 112.5 115.0 117.5 120.0 122.5 125.0 127.5 130.0 132.5 135.0 137.5 140.0 142.5 145.0 147.5 150.0 152.5 155.0 157.5 160.0 162.5 165 167.5 170 32 42.50 43.75 45.00 46.25 47.50 48.75 50.00 51.25 52.50 53.75 55.00 56.25 57.50 58.75 60.00 61.25 62.50 63.75 65.00 66.25 67.50 68.75 70.00 71.25 72.50 73.75 75.00 76.25 77.50 78.75^ 80.00 81.25 82.5 83.75 85.00 64 21.25 21.875 22.50 23.125 23.75 24.375 25.00 25.625 26.25 26.875 27.50 28.125 28.75 29.375 30.00 30.626 31.25 31.875 32.50 33.125 33.75 34.375 35.00 35.625 36.25 36.875 37.50 38.125 38.75 39.375 40.00 40.625 41.25 41.875 42.50 Freescale Semiconductor, Inc... 420 430 440 450 460 470 480 490 500 510 520 530 540 550 560 570 580 590 600 610 620 630 640 650 660 670 680 TIMING SOLUTIONS 15 MOTOROLA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MPC92432 VCC_PLL Filter The MPC92432 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCC_PLL pin impacts the device AC characteristics. The MPC92432 provides separate power supplies for the digital circuitry (VCC) and the internal PLL (VCC_PLL) of the device. The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In digital system environments where it is more difficult to minimize noise on the power supplies a second level of isolation is recommended: a power supply filter on the VCC_PLL pin for the MPC92432. RF = TBD CF = 22 F 10 nF Freescale Semiconductor, Inc... VCC VCC_PLL MPC92432. From the data sheet, the VCC_PLL current (the current sourced through the VCC_PLL pin) is maximum TBD mA, assuming that a minimum of TBD V must be maintained on the VCC_PLL pin. The resistor shown in Figure 8 must have a resistance of TBD to meet the voltage drop criteria. The minimum values for RF and the filter capacitor CF are defined by the filter characteristics: the RC filter should provide an attenuation greater than 40 dB for noise whose spectral content is above TBD kHz. In the recommended filter shown in Figure 7 the filter cut-off frequency is around 4.5 TBD and the noise attenuation at TBD KHz is better than TBD dB. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. MPC92432 VCC 7 33...100 nF Figure 7. VCC_PLL Power Supply Filter Figure 7 illustrates a recommended power supply filter scheme. The MPC9230 is most susceptible to noise with spectral content in the 1 kHz to 1 MHz range. Therefore, the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop that will be seen between the VCC supply and the VCC_PLL pin of the . AC Test Reference and Output Termination The MPC92432 LVPECL outputs are designed to drive 50 transmission lines and require a DC termination to VTT = VCC - 2 V. Figure 8 illustrates the AC test reference for the MPC92432 as used in characterization and test of this circuit. If a separate termination voltage (VTT) is not available, applications may use alternative output termination methods such as shown in Figure 9 and Figure 10. The high-speed differential output signals of the MPC92432 are incompatible to single-ended LVCMOS signals. In order to use the synthesizer in LVCMOS clock signal environments, the dual-channel translator device MC100ES60T23 provides the necessary level conversion. The MC100ES60T23 has been specifically designed to interface with the MPC92432 and supports clock frequency up to 180 MHz QA Pulse Generator Z = 50 fREF = 16 MHz Z = 50 QB RT = 50 Synthesizer Z = 50 Z = 50 DUT MPC92432 VTT RT = 50 Figure 8. MPC92432 AC Test Reference MOTOROLA 16 TIMING SOLUTIONS For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MPC92432 VCC 130 Qx Z = 50 QA VTT 50 Z = 50 MPC92432 82 QB Z = 50 Figure 9. Thevenin Termination MPC92432 VTT MC100ES60T23 Figure 11. Interfacing with LVCMOS Logic for Frequency < 180 MHz Freescale Semiconductor, Inc... Qx Z = 50 MPC92432 50 50 SMD Resistor Network 46.4 Figure 10. Resistor Network Termination TIMING SOLUTIONS 17 MOTOROLA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. OUTLINE DIMENSIONS FA SUFFIX 48-LEAD LQFP PACKAGE CASE 932-03 ISSUE F 4X 0.200 AB T-U Z 9 A1 48 37 A DETAIL Y P 1 36 Freescale Semiconductor, Inc... T B B1 12 25 U V AE V1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5m, 1994. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLAN AB IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS T, U, AND Z TO BE DETERMINED AT DATAUM PLANE AB. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE AC. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE AB. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL AE NOT CAUSE THE D DIMENSION TO EXCEED 0.350. 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076. 9. EXACT SHAPE OF EACH CORNER IS OPTIONAL. DIM A A1 B B1 C D E F G H J K L M N P R S S1 V V1 W AA MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.170 0.270 1.350 1.450 0.170 0.230 0.500 BSC 0.050 0.150 0.090 0.200 0.500 0.700 0 7 12 REF 0.090 0.160 0.250 BSC 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF 13 24 Z S1 S 4X T, U, Z DETAIL Y 0.200 AC T-U Z AB G 0.080 AC AD AC BASE METAL M TOP & BOTTOM R 0.250 C F D 0.080 M N J E AC T-U Z H W DETAIL AD AA K L SECTION AE-AE CASE 932 03 MOTOROLA 18 GAUGE PLANE TIMING SOLUTIONS For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. NOTES Freescale Semiconductor, Inc... TIMING SOLUTIONS 19 MOTOROLA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office. All other product or service names are the property of their respective owners. (c) Motorola, Inc. 2004 HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution P.O. Box 5405, Denver, Colorado 80217 1-800-521-6274 or 480-768-2130 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center 3-20-1 Minami-Azabu. Minato-ku, Tokyo 106-8573, Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong 852-26668334 HOME PAGE: http://motorola.com/semiconductors MPC92432 For More Information On This Product, Go to: www.freescale.com |
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